1.Field of the Invention
The present invention relates to a technology of highly integrated semiconductor memory and more specifically to a technology effectively applied to the disposition of a redundant memory cell and to a layout method of word drivers and sense amplifiers connected to the redundant memory cell.
2. Description of the Related Art
In the field of highly integrated semiconductor memories examined by the inventor, a technology of having a small number of redundant memory cells in addition to normal memory cells and of switching an access to the redundant memory cell when the normal memory cell is defective is widely used in order to improve the production yield.
As for the semiconductor memory having the redundant memory cells in addition to the normal memory cells as described above, there is a technology described in Japanese Patent Publication No. 2555252 entitled "Semiconductor Memory Device" for example. According to this technology, column redundancy is implemented by having a normal memory cell array and a redundant memory cell array in which a plurality of normal memory cell array blocks and a plurality of redundant memory cell array blocks are controlled in common by respective column decoders.
Noticing on the high integration of the semiconductor memory having the redundant memory cells in addition to the normal memory cells as described above, the inventor examined the disposition of the redundant memory cell and the layout method of word drivers and sense amplifiers connected to the redundant memory cell. The contents examined by the inventor will be explained below by using FIG. 10.
FIG. 10 shows the disposition of the redundant memory cell. This redundant memory cell is positioned at the peripheral part of a normal memory cell array 15 as shown in FIG. 10(a). Further, sense amplifier regions 16, sub-word driver regions 17 and their intersection regions 18 are disposed adjacent to and around the memory cell array 15 as shown in FIG. 10(b).
By the way, with the high integration of the semiconductor memory, while the plane size of the memory cell may be refined further by forming it in 3-D, direct peripheral circuits such as the word drivers and sense amplifiers connected with the memory cell must be reduced in the plane direction in correspondence to the memory cell. However, their layout is not easy because they are different from the memory cell and cannot be formed in 3-D.
Then, as a countermeasure thereof, there has been widely used a method of reducing an occupied area by sharing contacts, through holes, power sources and signal lines in a plurality of units of those circuits in a repeating pitch in which a plurality of memory cells are put together. For instance, it has been applied in the layout unit of word drivers corresponding to 16 word lines W and in the layout unit of sense amplifiers corresponding to 16 bit lines BL.
Meanwhile, along with the high integration of the memory, the yield of the redundant memory cell has also become a problem. Then, the redundant memory cell is disposed at the center of an array where the manufacturing condition is stable to make it alive. Because its test before setting a fuse may be eliminated or may be simplified if the redundant memory cell is surely alive, the whole test time may be shortened.
However, it has been difficult to lay out only the sub-word drivers or sense amplifiers related to the redundant memory cell specially because the number of word lines or bit lines of the redundant memory cell is smaller than the layout units. It is because the layout unit is too small so that the contacts, through holes, power sources and signal lines cannot be shared as described above. Further, there has been a possibility that the characteristics and yield of the sub-word drivers or sense amplifiers for the redundant memory cell become abnormal if the repeated shapes are different.